Espressif Systems /ESP32-P4 /I3C_MST /INT_ST_ENA

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Interpret as INT_ST_ENA

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_DATA_BUF_THLD_INT_ENA)TX_DATA_BUF_THLD_INT_ENA 0 (RX_DATA_BUF_THLD_INT_ENA)RX_DATA_BUF_THLD_INT_ENA 0 (IBI_STATUS_THLD_INT_ENA)IBI_STATUS_THLD_INT_ENA 0 (CMD_BUF_EMPTY_THLD_INT_ENA)CMD_BUF_EMPTY_THLD_INT_ENA 0 (RESP_READY_INT_ENA)RESP_READY_INT_ENA 0 (NXT_CMD_REQ_ERR_INT_ENA)NXT_CMD_REQ_ERR_INT_ENA 0 (TRANSFER_ERR_INT_ENA)TRANSFER_ERR_INT_ENA 0 (TRANSFER_COMPLETE_INT_ENA)TRANSFER_COMPLETE_INT_ENA 0 (COMMAND_DONE_INT_ENA)COMMAND_DONE_INT_ENA 0 (DETECT_START_INT_ENA)DETECT_START_INT_ENA 0 (RESP_BUF_OVF_INT_ENA)RESP_BUF_OVF_INT_ENA 0 (IBI_DATA_BUF_OVF_INT_ENA)IBI_DATA_BUF_OVF_INT_ENA 0 (IBI_STATUS_BUF_OVF_INT_ENA)IBI_STATUS_BUF_OVF_INT_ENA 0 (IBI_HANDLE_DONE_INT_ENA)IBI_HANDLE_DONE_INT_ENA 0 (IBI_DETECT_INT_ENA)IBI_DETECT_INT_ENA 0 (CMD_CCC_MISMATCH_INT_ENA)CMD_CCC_MISMATCH_INT_ENA

Description

The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.

Fields

TX_DATA_BUF_THLD_INT_ENA

Transmit Buffer threshold status enable.

RX_DATA_BUF_THLD_INT_ENA

Receive Buffer threshold status enable.

IBI_STATUS_THLD_INT_ENA

Only used in master mode. IBI Buffer threshold status enable.

CMD_BUF_EMPTY_THLD_INT_ENA

Command buffer ready status enable.

RESP_READY_INT_ENA

Response buffer ready status enable.

NXT_CMD_REQ_ERR_INT_ENA

next command request error status enable

TRANSFER_ERR_INT_ENA

Transfer error status enable

TRANSFER_COMPLETE_INT_ENA

NA

COMMAND_DONE_INT_ENA

NA

DETECT_START_INT_ENA

NA

RESP_BUF_OVF_INT_ENA

NA

IBI_DATA_BUF_OVF_INT_ENA

NA

IBI_STATUS_BUF_OVF_INT_ENA

NA

IBI_HANDLE_DONE_INT_ENA

NA

IBI_DETECT_INT_ENA

NA

CMD_CCC_MISMATCH_INT_ENA

NA

Links

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