The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.
| TX_DATA_BUF_THLD_INT_ENA | Transmit Buffer threshold status enable. |
| RX_DATA_BUF_THLD_INT_ENA | Receive Buffer threshold status enable. |
| IBI_STATUS_THLD_INT_ENA | Only used in master mode. IBI Buffer threshold status enable. |
| CMD_BUF_EMPTY_THLD_INT_ENA | Command buffer ready status enable. |
| RESP_READY_INT_ENA | Response buffer ready status enable. |
| NXT_CMD_REQ_ERR_INT_ENA | next command request error status enable |
| TRANSFER_ERR_INT_ENA | Transfer error status enable |
| TRANSFER_COMPLETE_INT_ENA | NA |
| COMMAND_DONE_INT_ENA | NA |
| DETECT_START_INT_ENA | NA |
| RESP_BUF_OVF_INT_ENA | NA |
| IBI_DATA_BUF_OVF_INT_ENA | NA |
| IBI_STATUS_BUF_OVF_INT_ENA | NA |
| IBI_HANDLE_DONE_INT_ENA | NA |
| IBI_DETECT_INT_ENA | NA |
| CMD_CCC_MISMATCH_INT_ENA | NA |